CPC H10K 59/131 (2023.02) [H10K 59/121 (2023.02); G09G 3/3208 (2013.01); G09G 2320/0209 (2013.01); G09G 2320/0233 (2013.01)] | 20 Claims |
1. A display substrate, providing with a display area and a peripheral area around the display area, and comprising: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein
in the peripheral area, the source/drain layer comprises at least one pair of first signal lines comprising a signal line of a gate circuit and the anode layer comprises a common power line provided with vent holes; and
overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer.
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