| CPC H10K 59/124 (2023.02) [H01L 29/78618 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01)] | 19 Claims |
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1. A display device comprising:
a base substrate;
a lower interlayer dielectric layer disposed on the base substrate;
an oxide semiconductor layer disposed on the lower interlayer dielectric layer and including a first channel region, a first drain region disposed on a first side of the first channel region, and a first source region disposed on a second side of the first channel region opposite to the first side of the first channel region;
a first gate insulating layer disposed on the oxide semiconductor layer;
a first upper gate electrode disposed on the first gate insulating layer;
an upper interlayer dielectric layer disposed on the first upper gate electrode;
a first source electrode and a first drain electrode disposed on the upper interlayer dielectric layer;
a first lower gate electrode disposed between the base substrate and the oxide semiconductor layer;
a capacitor electrode disposed on a same first layer as the first lower gate electrode and spaced apart from the first lower gate electrode;
an upper gate insulating layer disposed between the capacitor electrode and the base substrate; and
a second gate electrode disposed between the upper gate insulating layer and the base substrate,
wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer,
wherein the first lower interlayer dielectric layer includes silicon nitride, and the second lower interlayer dielectric layer includes silicon oxide,
wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89, and
wherein the second gate electrode underlaps the capacitor electrode.
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