US 12,108,609 B1
Memory bit-cell with stacked and folded planar capacitors
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 7, 2022, as Appl. No. 17/653,811.
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); G11C 11/22 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 11/223 (2013.01); G11C 11/221 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; and
a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, wherein the plurality of capacitors are planar capacitors that are arranged in a stacked and folded configuration, wherein the individual capacitor includes a top electrode which is coupled to the individual plate-line, and wherein the top electrode is coupled to the individual plate-line with a pedestal.