	US 12,108,608 B1
	Memory devices with dual encapsulation layers and methods of fabrication
Noriyuki Sato, Hillsboro, OR (US); Debraj Guhabiswas, Berkeley, CA (US); Tanay Gosavi, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 15, 2021, as Appl. No. 17/503,009.
Application 17/503,009 is a continuation of application No. 17/449,750, filed on Oct. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); H01L 49/02 (2006.01)

CPC H10B 53/30 (2023.02) [H01L 28/60 (2013.01)]

20 Claims

1. A method of fabricating a device structure, the method comprising:

forming a first conductive interconnect adjacent to a dielectric in a memory region and a second conductive interconnect adjacent to the dielectric in a logic region;

depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect;

forming an electrode structure on the first conductive interconnect by etching a first opening in the etch stop layer and depositing a first conductive material;

forming a memory device on the electrode structure, wherein forming the memory device comprises:

depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure; and

etching the material layer stack to form a first recessed surface in the etch stop layer in the memory region and in the logic region;

forming a spacer on a first sidewall of the memory device by depositing a first encapsulation layer and etching the first encapsulation layer, wherein etching the first encapsulation layer substantially removes the first encapsulation layer adjacent to the spacer and from the logic region, and wherein etching the first encapsulation layer further comprises forming a second sidewall and a second recessed surface in the etch stop layer, wherein the second sidewall is substantially aligned with an outer sidewall of the spacer;

depositing a second encapsulation layer on the memory device, on the spacer in the memory region and in the logic region, wherein depositing the second encapsulation layer comprises depositing on the second sidewall and on a portion of the second recessed surface;

depositing a dielectric layer on the second encapsulation layer;

forming a via electrode on the memory device by forming a second opening in the dielectric layer and in the second encapsulation layer and depositing a second conductive material in the second opening; and

simultaneously forming a via structure on the second conductive interconnect and a metal line on the via structure by patterning a third opening in the dielectric and in the second encapsulation layer.