| CPC H10B 53/30 (2023.02) [H01L 28/60 (2013.01); H10B 53/40 (2023.02)] | 21 Claims |
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1. A device comprising:
a first region comprising:
a first conductive interconnect comprising a cylindrical shape;
a plurality of memory devices above the first conductive interconnect, wherein a first memory device in the plurality of memory devices is above the first conductive interconnect, and wherein the plurality of memory devices comprises a ferroelectric material or paraelectric material;
an electrode structure coupled with the plurality of memory devices, and between the first conductive interconnect and the first memory device;
a barrier layer comprising a dielectric material, the barrier layer laterally adjacent to the electrode structure, wherein the barrier layer comprises a first surface and a second surface, wherein the second surface is recessed relative to the first surface;
a spacer on a sidewall of the plurality of memory devices, wherein the spacer extends below an interface between the plurality of memory devices and the electrode structure on to a portion of the second surface; and
a via electrode on each of the plurality of memory devices; and
a second region adjacent to the first region, the second region comprising:
a second conductive interconnect at a same level as the first conductive interconnect;
a metal line above the second conductive interconnect; and
a via structure between the second conductive interconnect and the metal line, wherein at least a second portion of the via structure is adjacent to the barrier layer, and wherein the barrier layer is on at least a third portion of the second conductive interconnect.
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