a substrate having an upper surface;

a gate structure disposed over the substrate, the gate structure comprising at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface, wherein the gate structure extends in a second direction perpendicular to the first direction;

a ferroelectric layer disposed over the substrate and disposed on at least a portion of one sidewall surface of the gate structure, wherein the one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions;

a channel layer disposed over the substrate and disposed on the ferroelectric layer;

a source electrode structure and a drain electrode structure, spaced apart from each other in the second direction, each disposed over the substrate and disposed to contact the channel layer;

an insulation structure disposed between the source electrode structure and the drain electrode structure, the insulation structure disposed to contact the channel layer and extending in the first direction; and

a non-ferroelectric first interfacial insulation layer disposed between the ferroelectric layer and the channel layer.