US 12,108,599 B2
Semiconductor memory device and a method of manufacturing the same
Geun-won Lim, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 6, 2023, as Appl. No. 18/206,402.
Application 18/206,402 is a division of application No. 17/490,080, filed on Sep. 30, 2021, granted, now 11,706,923.
Application 17/490,080 is a continuation of application No. 16/512,862, filed on Jul. 16, 2019, granted, now 11,152,387, issued on Oct. 19, 2021.
Claims priority of application No. 10-2018-0162155 (KR), filed on Dec. 14, 2018.
Prior Publication US 2023/0320098 A1, Oct. 5, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a common source line and a substrate on a peripheral circuit including a peripheral transistor;
forming a preliminary stack structure that includes sacrificial films and insulation films alternately stacked in a vertical direction on the substrate;
forming first and second word line cuts that extend in a first horizontal direction on the substrate and penetrate the preliminary stack structure in the vertical direction, the first word line cuts having a different length than the second word line cuts in the first horizontal direction; and
forming a box structure that is apart from both the first and the second word line cuts by a first distance by replacing a portion of each of the sacrificial films that is within the first distance from the first and the second word line cuts with a gate electrode.