| CPC H10B 41/27 (2023.02) [G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H01L 2224/06181 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1451 (2013.01)] | 20 Claims |
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1. A semiconductor structure, comprising:
a memory die bonded to a logic die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers;
a semiconductor material layer located over a distal surface of the alternating stack, wherein the semiconductor material layer is more distal from the logic die than the alternating stack is from the logic die;
a dielectric spacer layer located over a distal surface of the semiconductor material layer;
memory openings vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer;
memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film; and
a source layer located over a distal surface of the dielectric spacer layer and contacting the pillar portions of the vertical semiconductor channels.
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