US 12,108,595 B2
Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication
Sumit Ashtekar, Portland, OR (US); Rahul Ramaswamy, Portland, OR (US); Walid Hafez, Portland, OR (US); and Hector M. Saavedra Garcia, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 24, 2020, as Appl. No. 17/001,525.
Prior Publication US 2022/0059552 A1, Feb. 24, 2022
Int. Cl. H01L 21/8238 (2006.01); H01H 85/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 20/20 (2023.01)
CPC H10B 20/20 (2023.02) [H01H 85/0241 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01H 2085/0283 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device structure comprising:
a first gate on a first fin;
a second gate on a second fin, wherein the second gate is spaced apart from the first gate by a distance;
a fuse spanning the distance and in contact with the first gate and the second gate;
a first dielectric between the first fin and the second fin, wherein the first dielectric is in contact with, and below, the fuse; and
a second dielectric between the first gate and the second gate, wherein the second dielectric is on the fuse.