| CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); G11C 11/4096 (2013.01)] | 5 Claims |
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1. A memory device through use of a semiconductor device, including a plurality of pages arrayed in a column direction, each of the pages being composed of a plurality of memory cells arrayed on a substrate in a row direction, wherein
each of the memory cells included in each of the pages has,
a semiconductor base standing in a vertical direction or extending in a horizontal direction on the substrate with respect to the substrate,
a first impurity layer and a second impurity layer located on opposite ends of the semiconductor base,
a first gate insulating layer that surrounds part or whole of a side surface of the semiconductor base between the first impurity layer and the second impurity layer, and is in contact with or proximate to the first impurity layer,
a second gate insulating layer that surrounds the side surface of the semiconductor base, connects to the first gate insulating layer, and is in contact with or proximate to the second impurity layer,
a first gate conductor layer that covers part or whole of the first gate insulating layer,
a second gate conductor layer that covers the second gate insulating layer, and
a channel semiconductor layer in which the semiconductor base is covered by the first gate insulating layer and the second gate insulating layer,
the memory device controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region to perform a page write operation and a page erase operation,
the first impurity layer of the each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line,
the bit line is connected to a forced inversion type sense amplifier circuit via a switching circuit, and
when in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the forced inversion type sense amplifier circuit.
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