| CPC H04N 25/585 (2023.01) [H04N 25/59 (2023.01); H04N 25/616 (2023.01); H04N 25/709 (2023.01); H04N 25/75 (2023.01); H04N 25/77 (2023.01); H04N 25/78 (2023.01)] | 13 Claims |
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1. An image sensor comprising:
a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and sequentially output, as a pixel voltage, an LCG reset signal, an HCG reset signal, an HCG image signal, and an LCG image signal;
a correlated double sampling (CDS) circuit configured to compare a ramp signal to the pixel voltage received from the pixel and generate a comparison signal; and
a counter circuit configured to generate an HCG pixel value and an LCG pixel value based on the comparison signal received from the CDS circuit and a counting code, the counting code having a code value that increases over time,
wherein the counter circuit comprises:
a latch configured to latch the code value of the counting code at a time when a level of the comparison signal transitions, and output the code value as a counting value with respect to the comparison signal;
a first memory configured to store a first counting value output from the latch;
a second memory configured to store a second counting value output from the latch after the first counting value is output;
a selector connected to the first memory and the second memory; and
a calculator configured to perform calculation on one of a third counting value and a fourth counting value output from the latch and one of the first counting value and the second counting value, received from the selector.
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