| CPC H04N 19/423 (2014.11) [H04N 19/146 (2014.11); H04N 19/176 (2014.11)] | 15 Claims |
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1. A video processing circuit generating a video stream and coupled to an external memory which stores partial data of a first frame, the video processing circuit comprising:
a memory;
a control circuit configured to read a first image block from the external memory and store the first image block in the memory, the first image block being a part of the first frame;
an image processing circuit configured to read the first image block from the memory and process the first image block to generate a second image block, wherein the second image block is a part of a second frame which is different from the first frame; and
a video encoding circuit configured to read the first image block from the memory and encode the first image block to generate a part of the video stream;
wherein the image processing circuit further stores the second image block in the external memory, and the control circuit further reads the second image block from the external memory and stores the second image block in the memory;
wherein the video stream is a first video stream, the video processing circuit further generates a second video stream and a third video stream in sequence, and the image processing circuit and the video encoding circuit determine whether to process or encode the second image block according to a frame rate of the second video stream and a frame rate of the third video stream.
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