CPC H04N 19/105 (2014.11) [H04N 19/172 (2014.11); H04N 19/46 (2014.11); H04N 19/70 (2014.11)] | 3 Claims |
1. A device comprising one or more processors configured to:
decode a flag in a reference picture list structure, wherein the flag specifies whether long-term reference picture Picture Order Count (POC) least significant bit (LSB) information is signaled;
decode the long-term reference picture POC LSB information in the reference picture list structure or in a slice header according to a value of the flag;
decode a number of entries syntax element in the reference picture list structure;
decode a number of reference index active minus one syntax element in the slice header, in a case that a value of the number of entries syntax element is greater than a first value; and
derive a variable by using the number of reference index active minus one syntax element.
|