	US 12,107,788 B2
	Multiplexing synchronization signal blocks, control resource set, and system information blocks
Qingjiang Tian, San Diego, CA (US); Jing Sun, San Diego, CA (US); Xiaoxia Zhang, San Diego, CA (US); Zhifei Fan, San Diego, CA (US); Iyab Issam Sakhnini, San Diego, CA (US); Wooseok Nam, San Diego, CA (US); and Tao Luo, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Dec. 7, 2021, as Appl. No. 17/643,142.
Claims priority of provisional application 63/199,679, filed on Jan. 15, 2021.
Prior Publication US 2022/0231811 A1, Jul. 21, 2022
Int. Cl. H04W 56/00 (2009.01); H04L 5/00 (2006.01)

CPC H04L 5/0048 (2013.01) [H04L 5/0094 (2013.01)]

6 Claims

1. A method of wireless communication performed by a user equipment (UE), the method comprising:

receiving, from a base station (BS), a first synchronization signal block (SSB) of a first group of SSBs of an SSB burst set, wherein the first group of SSBs and a second group of SSBs of the SSB burst set are spaced apart in time by a group of control resource sets (CORESETs) and system information blocks (SIBs), wherein the group of CORESETs and SIBs comprises one CORESET and at least one SIB for each SSB of the first group of SSBs;

receiving, in a first CORESET of the group of CORESETs and SIBs based on the first SSB, SIB scheduling information;

receiving, based on the SIB scheduling information, a first SIB of the group of CORESETs and SIBs;

wherein the first group of SSBs and the second group of SSBs are associated with a first subcarrier spacing (SCS), and wherein the group of CORESETs and SIBs is associated with a second SCS different from the first SCS;

wherein the group of CORESETs and SIBs is in consecutive slots, wherein the consecutive slots are based on the second SCS, and wherein each consecutive slot includes two CORESETs and two SIBs of the group of CORESETs and SIBs;

wherein the first SCS is 120 kilohertz (kHz), and wherein the second SCS is 480 kHz;

determining a slot index n_cfor the first CORESET based on the second SCS in accordance with the following:

and

wherein i is an SSB index associated with the first SSB and n_iis a slot index associated with the first SSB based on the second SCS.