CPC H04L 49/50 (2013.01) [H04L 47/125 (2013.01); H04L 47/726 (2013.01); H04L 45/74 (2013.01)] | 17 Claims |
1. A switch comprising:
at least one processor;
a ternary content-addressable memory; and
a memory storing instructions which when executed by the at least one processor, causes the at least one processor to:
receive an incoming network packet;
identify whether to load balance the incoming network packet across a plurality of service nodes;
in response to identifying whether to load balance the incoming network packet, mask, by a bitmask, a portion of a source address of the incoming network packet to expose a fragment of the source address;
adjust the bitmask to select the specific number of bits of the source address to be masked; and
assign the incoming network packet to a service node of the plurality of service nodes by identifying an address of the service node from the fragment of the source address based on a mapping of fragments of source addresses to addresses of traffic buckets of the plurality of service nodes within a routing table, wherein the mapping is stored at the ternary content-addressable memory.
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