US 12,107,776 B2
Adjustable bit mask for high-speed native load balancing on a switch
Rajendra Kumar Thirumurthi, Cupertino, CA (US); Samar Sharma, San Jose, CA (US); and Mouli Vytla, San Jose, CA (US)
Assigned to Cisco Technology, Inc., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Jul. 11, 2022, as Appl. No. 17/862,043.
Application 17/862,043 is a continuation of application No. 16/420,009, filed on May 22, 2019, granted, now 11,388,113.
Application 16/420,009 is a continuation of application No. 14/715,339, filed on May 18, 2015, granted, now 10,305,816, issued on May 28, 2019.
Claims priority of provisional application 62/141,158, filed on Mar. 31, 2015.
Prior Publication US 2022/0345422 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 49/50 (2022.01); H04L 45/74 (2022.01); H04L 47/125 (2022.01); H04L 47/726 (2022.01)
CPC H04L 49/50 (2013.01) [H04L 47/125 (2013.01); H04L 47/726 (2013.01); H04L 45/74 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A switch comprising:
at least one processor;
a ternary content-addressable memory; and
a memory storing instructions which when executed by the at least one processor, causes the at least one processor to:
receive an incoming network packet;
identify whether to load balance the incoming network packet across a plurality of service nodes;
in response to identifying whether to load balance the incoming network packet, mask, by a bitmask, a portion of a source address of the incoming network packet to expose a fragment of the source address;
adjust the bitmask to select the specific number of bits of the source address to be masked; and
assign the incoming network packet to a service node of the plurality of service nodes by identifying an address of the service node from the fragment of the source address based on a mapping of fragments of source addresses to addresses of traffic buckets of the plurality of service nodes within a routing table, wherein the mapping is stored at the ternary content-addressable memory.