a first delay circuit configured to delay a first input signal to generate a delayed first input signal;

a second delay circuit configured to delay a second input signal to generate a delayed second input signal;

a first programmable time difference amplifier configured to apply a gain value to the delay between the first input signal and the delayed first input signal to generate an amplified delayed first input signal, which is feedback to the first delay circuit and the first programmable time difference amplifier;

a second programmable time difference amplifier configured to apply a gain value to the delay between the second input signal and the delayed second input signal to generate an amplified delayed second input signal, which is feedback to the second delay circuit and the second programmable time difference amplifier;

a comparator configured to determine a bit value for a step in a N step conversion, the bit value based on which of the amplified delayed first input signal and the amplified delayed second input signal is in leading position; and

a finite state machine configured to set another gain value, for a next step in the N step conversion, in the first programmable time difference amplifier based on the determined bit value in a previous step and set another gain value in the second programmable time difference amplifier based on the determined bit value in the previous step,

wherein the N-bit successive approximation register based time-to-digital converter is configured to