US 12,107,595 B2
Comparator and analog-to-digital converter
Yuki Yagishita, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/906,663
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Mar. 23, 2021, PCT No. PCT/JP2021/012087
§ 371(c)(1), (2) Date Sep. 19, 2022,
PCT Pub. No. WO2021/200416, PCT Pub. Date Oct. 7, 2021.
Claims priority of application No. 2020-061363 (JP), filed on Mar. 30, 2020.
Prior Publication US 2023/0179220 A1, Jun. 8, 2023
Int. Cl. H03M 1/00 (2006.01); H03M 1/46 (2006.01); H03M 1/66 (2006.01); H03M 1/72 (2006.01)
CPC H03M 1/46 (2013.01) [H03M 1/662 (2013.01); H03M 1/72 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A comparator, comprising:
a first input terminal and a second input terminal configured to receive a first differential input signal pair;
a third input terminal and a fourth input terminal configured to receive a second differential input signal pair;
a first comparison circuit configured to output a first signal corresponding to:
a difference signal of the first differential input signal pair based on connection of the first input terminal to a positive side and connection of the second input terminal to a negative side, and
a difference signal of the second differential input signal pair based on connection of the third input terminal to the positive side and connection of the fourth input terminal to the negative side; and
a second comparison circuit configured to output a second signal corresponding to:
a difference signal of the first differential input signal pair based on connection of the first input terminal to the negative side and connection of the second input terminal to the positive side, and
a difference signal of the second differential input signal pair based on connection of the third input terminal to the positive side and connection of the fourth input terminal to the negative side.