| CPC H03L 7/0991 (2013.01) [H03B 5/32 (2013.01)] | 24 Claims |
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1. An apparatus comprising:
a fractional-N phase-locked loop (PLL) to generate an output signal having one of a plurality of output frequencies, the fractional-N PLL including,
an oscillator;
a phase detector to receive a reference clock signal and a feedback signal; and
a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector; and
a multi-modulus pattern generator to supply a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal, the multi-modulus pattern generator initiating the drive pattern at a boundary time to cause the output signal to have a repeatable phase when switching from any one of the output frequencies to any other of the output frequencies.
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