an input node configured to receive a clock signal having a clock period;

a reference node configured to receive a reference clock signal;

a delay line coupled to the reference node to receive the reference clock signal, the delay line configured to produce a set of delayed replicas of the reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween;

a set of edge detecting stages coupled to the input node and to the delay line, the set of edge detecting stages configured to produce a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of the clock signal;

selecting circuitry coupled to set of edge detecting stages and configured to select, based on edge detecting signals in the set of edge detecting signals, a delayed replica in the set of delayed replicas having a distance from a respective clock signal edge that is shorter than the distance from any other clock signal edge of any other delayed replica in the set of delayed replicas; and

comparator circuitry coupled to the selecting circuitry to receive the selected delayed replica and to the input node to receive the clock signal, the comparator circuitry configured to perform a comparison of the clock period of the clock signal and of the selected delayed replica, obtaining as a result of the comparison, an error signal indicative of a difference therebetween,

wherein the comparator circuitry is configured to provide the error signal to user circuitry to calibrate the clock signal based on the error signal.