US 12,107,556 B2
Fault detection in integrated circuits
Sanjay Sunder, Allentown, PA (US); Alexander C. Kurylak, Bethlehem, PA (US); and Kadaba Lakshmikumar, Basking Ridge, NJ (US)
Assigned to Cisco Technology, Inc., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/448,822.
Prior Publication US 2023/0100245 A1, Mar. 30, 2023
Int. Cl. H03F 3/45 (2006.01); H03G 3/30 (2006.01)
CPC H03F 3/45475 (2013.01) [H03G 3/30 (2013.01); H03G 2201/103 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a transimpedance amplifier;
a first injection circuit configured to:
generate a first electrical test signal; and
inject the first electrical test signal into the transimpedance amplifier; and
a second injection circuit configured to inject a second electrical test signal into the transimpedance amplifier, wherein the first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.