US 12,107,552 B2
Power amplifier management
Earl Schreyer, Raleigh, NC (US); Sherif Galal, Irvine, CA (US); Sang-Uk Ryu, San Diego, CA (US); Hui-ya Liao Nelson, San Diego, CA (US); Subbarao Surendra Chakkirala, San Jose, CA (US); and Shreyas Srikanth Payal, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 21, 2021, as Appl. No. 17/448,244.
Prior Publication US 2023/0108378 A1, Apr. 6, 2023
Int. Cl. G06K 7/10 (2006.01); H03F 1/02 (2006.01); H03F 3/24 (2006.01)
CPC H03F 1/0227 (2013.01) [H03F 3/245 (2013.01); H03F 2200/03 (2013.01); H03F 2200/462 (2013.01); H03F 2200/468 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A device comprising:
a memory; and
one or more processors coupled to the memory, the one or more processors configured to:
receive first data associated with a first power amplifier and second data associated with a second power amplifier;
generate a first amplitude limiting signal having gain parameters that are based on the first data and the second data, the first data comprising at least one of a temperature measurement associated with the first power amplifier, a supply voltage measurement associated with the first power amplifier, a load resistance associated with the first power amplifier, or a gain associated with the first power amplifier;
modify an audio signal based at least in part on the first amplitude limiting signal to generate a first gain-adjusted audio signal; and
provide a first output audio signal to the first power amplifier for amplification, the first output audio signal based at least in part on the first gain-adjusted audio signal.