| CPC H01L 29/7869 (2013.01) [G11C 5/063 (2013.01); G11C 11/405 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); H01L 29/78696 (2013.01); H10B 12/50 (2023.02)] | 10 Claims |
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1. A memory device comprising:
a memory cell array comprising a plurality of memory cells; and
a peripheral circuit,
wherein each of the memory cells is electrically connected to first to fifth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein each of the first transistor and the second transistor comprises a front gate and a back gate,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the front gate of the second transistor,
wherein the front gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein the back gate of the second transistor is electrically connected to the back gate of the first transistor,
wherein the back gate of the first transistor is electrically connected to the fifth wiring supplied with a predetermined potential,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region,
wherein the peripheral circuit comprises a first circuit, a second circuit, and a controller,
wherein the first circuit is electrically connected to the first wiring and the second wiring,
wherein the first circuit is configured to write data to the memory cell and is configured to read data from the memory cell,
wherein the second circuit is electrically connected to the third wiring and the fourth wiring,
wherein the second circuit is configured to drive the third wiring and the fourth wiring, and
wherein the controller is configured to control the first circuit and the second circuit.
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