US 12,107,170 B2
Transistor channel passivation with 2D crystalline material
Carl Naylor, Portland, OR (US); Abhishek Sharma, Hillsboro, OR (US); Mauro Kobrinsky, Portland, OR (US); Christopher Jezewski, Portland, OR (US); Urusa Alaan, Hillsboro, OR (US); and Justin Weber, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 2, 2021, as Appl. No. 17/517,583.
Application 17/517,583 is a continuation of application No. 16/570,965, filed on Sep. 13, 2019, granted, now 11,171,239.
Prior Publication US 2022/0059702 A1, Feb. 24, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78609 (2013.01) [H01L 27/1207 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A transistor structure, comprising:
a channel material comprising oxygen and a metal;
a source contact and a drain contact in direct contact with the channel material;
a gate stack over a first region of the channel material, where the gate stack comprises a gate electrode material and a gate insulator, and wherein the gate insulator is in direct contact with the first region of the channel material; and
a material comprising a metal and a chalcogen in direct contact with a second region of the channel material, the material comprising the metal and the chalcogen between the gate stack and each of the source contact and the drain contact.