US 12,107,168 B2
Independent gate length tunability for stacked transistors
Ruqiang Bao, Niskayuna, NY (US); Junli Wang, Slingerlands, NY (US); and Dechao Guo, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,618.
Prior Publication US 2023/0068484 A1, Mar. 2, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/7855 (2013.01) [H01L 29/0665 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a bottom field effect transistor (FET) and a top FET stacked in a vertical manner one atop the other and separated by an insulator structure, wherein the bottom FET has a first gate length, and the top FET has a second gate length that differs from the first gate length, wherein the bottom FET is a FinFET, and the top FET is a nanosheet FET and wherein the FinFET comprises a semiconductor fin embedded in the insulator structure, and wherein the FinFET comprises a first functional gate structure located beneath the semiconductor fin; and
a dielectric bonding layer located beneath the FinFET and spaced apart from the insulator structure, wherein the dielectric bonding layer is in direct physical contact with a first gate electrode of the first functional gate structure of the FinFET.