US 12,107,167 B2
High-threshold power semiconductor device and manufacturing method thereof
Siyang Liu, Nanjing (CN); Weifeng Sun, Nanjing (CN); Chi Zhang, Nanjing (CN); Shuxuan Xin, Nanjing (CN); Shen Li, Nanjing (CN); Le Qian, Nanjing (CN); Chen Ge, Nanjing (CN); and Longxing Shi, Nanjing (CN)
Assigned to SOUTHEAST UNIVERSITY, Jiangsu (CN)
Appl. No. 17/762,929
Filed by SOUTHEAST UNIVERSITY, Nanjing (CN)
PCT Filed Jan. 20, 2021, PCT No. PCT/CN2021/072830
§ 371(c)(1), (2) Date Mar. 23, 2022,
PCT Pub. No. WO2022/062281, PCT Pub. Date Mar. 31, 2022.
Claims priority of application No. 202011036591.X (CN), filed on Sep. 27, 2020.
Prior Publication US 2022/0367716 A1, Nov. 17, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/778 (2006.01); H01L 29/812 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 29/1095 (2013.01); H01L 29/778 (2013.01); H01L 29/8122 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A high-threshold power semiconductor device, comprising:
a metal drain electrode, a substrate, a buffer layer and a drift region which are stacked from bottom to top, wherein a drift region protrusion protrudes from a partial region of the drift region;
a columnar p-region and a columnar n-region are provided on the drift region protrusion in sequence;
a composite column body is formed by the drift region protrusion, the columnar p-region and the columnar n-region;
a channel layer is provided on an upper surface of the drift region, an outer side of the composite column body and a top of the composite column body;
a passivation layer is provided on a bottom surface of the channel layer;
a part of the drift region and a part of the channel layer, the passivation layer and the composite column body thereon are classified into a cell region;
the other part of the drift region and a part of the channel layer, the passivation layer and the composite column body thereon are classified into a terminal region;
a dielectric layer is provided on a surface of the passivation layer in the cell region and an outer side of the channel layer;
a metal gate electrode is provided on an outer side of the dielectric layer;
a heavily doped semiconductor layer is provided on a top surface of the channel layer in the cell region;
a source metal electrode is provided on the heavily doped semiconductor layer;
the passivation layer in the terminal region extends and is wrapped outside the channel layer in the terminal region.