US 12,107,158 B2
SiC-mosfet
Katsutoshi Sugawara, Tokyo (JP); Yasuhiro Kagawa, Tokyo (JP); and Yutaka Fukui, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Nov. 23, 2021, as Appl. No. 17/456,250.
Claims priority of application No. 2021-037173 (JP), filed on Mar. 9, 2021.
Prior Publication US 2022/0293783 A1, Sep. 15, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01)
CPC H01L 29/7805 (2013.01) [H01L 29/0623 (2013.01); H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/7811 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An SiC-MOSFET, comprising:
an SiC substrate of a first conductivity type;
a drift layer of a first conductivity type formed on the SiC substrate;
a base region of a second conductivity type formed on a surface layer of the drift layer;
a source region of a first conductivity type formed on a surface layer of the base region;
a gate electrode facing a channel region which is a region of the base region sandwiched between the drift layer and the source region via a gate insulating film;
a source electrode having electrical contact with the source region; and
a plurality of first embedded regions of a second conductivity type formed adjacent to and directly contacting a lower surface of the base region, wherein
two of the plurality of first embedded regions are respectively positioned immediately below outermost opposing end portions of the base region such that each of the two of the plurality of first embedded regions has a side substantially vertically aligned with one of the outermost opposing end portions of the base region, and
three or more of the plurality of first embedded regions are formed to be separated from each other.