	US 12,107,146 B2
	Self-aligned air spacers and methods for forming
Huan-Chieh Su, Hsinchu (TW); Jia-Chuan You, Hsinchu (TW); Cheng-Chi Chuang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 5, 2021, as Appl. No. 17/394,982.
Prior Publication US 2023/0043669 A1, Feb. 9, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)

CPC H01L 29/66545 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)]

20 Claims

1. A method of manufacturing a semiconductor device comprising:

forming a first dummy gate and a second dummy gate on a semiconductor substrate;

depositing a sidewall layer on the first and second dummy gates;

depositing a first dummy spacer layer on the sidewall layer;

depositing a first interlayer dielectric (ILD) layer on the first dummy spacer layer;

removing upper portions of the first ILD layer, the first dummy spacer layer, and the sidewall layer, to form residual portions of the first ILD layer, residual portions of the first dummy spacer layer, and residual portions of the sidewall layer;

removing first portions of the first and second dummy gates to form first and second residual dummy gates;

removing portions of the residual portions of the first dummy spacer layer to form first dummy spacers having a first height DS_H1and a first width DS_W1and the residual portions of the sidewall layer to form sidewalls having a sidewall height SW_H1and a sidewall width SW_W1, wherein top surfaces of the first and second residual dummy gates, first dummy spacers, and sidewalls are coplanar;

removing the first and second residual dummy gates to open exposed regions of the semiconductor substrate;

constructing a gate structure on the exposed regions of the semiconductor substrate and between the sidewalls, the gate structure having a height GS_H1, wherein GS_H1<SW_H1;

depositing a second dummy layer;

removing a first portion of the second dummy layer to form second dummy spacers on the first dummy spacers, the second dummy spacers having a second dummy spacer height DSH2 and a second dummy spacer width DS_W2;

depositing a first self-aligned contact layer (SAC1);

removing an upper portion of the SAC1 to expose upper surfaces of the residual portions of the first ILD layer;

removing the residual portions of the first ILD layer and an additional portion of the SAC1 to expose upper surfaces of the second dummy spacers;

removing the second dummy spacers to define an upper recess having an upper recess depth UR_D1and an upper recess width UR_W1, and to expose an upper surface of the first dummy spacer;

removing the first dummy spacers to define a lower recess having a lower recess depth LR_D1and a lower recess width LR_W1; and

forming a plug in the upper recess to cap the lower recess and define an air spacer, the air spacer having a spacer depth SP_D1and a spacer width SP_W1.