	US 12,107,144 B2
	Threshold adjustment for quantum dot array devices with metal source and drain
John H. Zhang, Altamont, NY (US)
Assigned to STMICROELECTRONICS, INC., Coppell, TX (US)
Filed by STMICROELECTRONICS, INC., Coppell, TX (US)
Filed on Jan. 12, 2022, as Appl. No. 17/574,329.
Application 17/574,329 is a division of application No. 16/025,982, filed on Jul. 2, 2018, granted, now 11,264,480.
Application 14/982,316 is a division of application No. 13/931,234, filed on Jun. 28, 2013, granted, now 9,748,356, issued on Aug. 29, 2017.
Application 16/025,982 is a continuation of application No. 14/982,316, filed on Dec. 29, 2015, granted, now 10,038,072, issued on Jul. 31, 2018.
Claims priority of provisional application 61/705,612, filed on Sep. 25, 2012.
Prior Publication US 2022/0140110 A1, May 5, 2022
Int. Cl. H01L 29/45 (2006.01); H01L 21/265 (2006.01); H01L 21/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/41 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01)

CPC H01L 29/66492 (2013.01) [H01L 21/26513 (2013.01); H01L 21/823814 (2013.01); H01L 22/12 (2013.01); H01L 29/413 (2013.01); H01L 29/456 (2013.01); H01L 29/66431 (2013.01); H01L 29/66666 (2013.01); H01L 29/775 (2013.01); H01L 29/7781 (2013.01); H01L 21/823842 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/4975 (2013.01); H01L 2924/0002 (2013.01)]

19 Claims

1. A method, comprising:

forming a first recess in a substrate;

forming a second recess in the substrate adjacent to a first side of the first recess;

forming a third recess in the substrate adjacent to a second side of the first recess, the second side of the first recess being opposite the first side of the first recess;

forming, in a same first deposition process, a first metal layer in the first recess, a second metal layer in the second recess, and a third metal layer in the third recess;

forming a gate region including the first metal layer in the first recess;

forming a source region in the second recess and a drain region in the third recess by:

forming, from the second metal layer, a first silicide layer on sidewalls and a bottom of the second recess;

forming, from the third metal layer, a second silicide layer on sidewalls and a bottom of the third recess;

forming, in a same second deposition process, first metal quantum dot on the first silicide layer, second metal quantum dot on the second silicide layer, a metal gate in the third recess on the first metal layer; and

forming a first surface by planarizing a surface of the substrate, the gate region, the source region, and the drain region, the first surface being planar and including a first surface of the substrate, a first surface of the gate region, a first surface of the source region, and a first surface of the drain region.