| CPC H01L 29/516 (2013.01) [H01L 23/5226 (2013.01); H01L 27/0886 (2013.01); H01L 28/40 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate including an active region and a field region defining the active region;
a plurality of fin patterns disposed on the active region of the substrate and extending along in a first direction;
a gate structure on the plurality of fin patterns, the gate structure including a gate spacer and a gate electrode, the gate electrode extending in a second direction and having a first portion on the active region of the substrate and a second portion on the field region of the substrate;
a first conductive connection group on the gate electrode of the gate structure, the first conductive connection group including a ferroelectric material layer;
a source/drain pattern disposed on the plurality of fin patterns; and
a second conductive connection group connected to the source/drain pattern,
wherein at least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer,
wherein the first conductive connection group includes a gate contact plug being in contact with at least a portion of the first portion of the gate electrode, and
wherein a width of the gate contact plug in the second direction is smaller than a width of the first portion of the gate electrode in the second direction.
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