US 12,107,137 B2
Semiconductor device
Mitsuru Okigawa, Kyoto (JP); Fujio Okui, Kyoto (JP); Yasushi Higuchi, Kyoto (JP); Koji Amazutsumi, Kyoto (JP); Hidetaka Shibata, Kyoto (JP); Yuji Kato, Kyoto (JP); and Atsushi Terai, Kyoto (JP)
Assigned to FLOSFIA INC., Kyoto (JP)
Filed by FLOSFIA INC., Kyoto (JP)
Filed on Jun. 7, 2022, as Appl. No. 17/834,089.
Claims priority of application No. 2021-095499 (JP), filed on Jun. 7, 2021; and application No. 2022-089958 (JP), filed on Jun. 1, 2022.
Prior Publication US 2022/0393015 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 29/47 (2006.01); H01L 29/872 (2006.01)
CPC H01L 29/475 (2013.01) [H01L 29/0649 (2013.01); H01L 29/872 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising at least:
an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component;
an n−-type semiconductor layer that is placed on the n+-type semiconductor layer, the n−-type semiconductor layer containing a crystalline oxide semiconductor as a major component;
a high-resistance layer with at least a part thereof being embedded in the n−-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 μm from an upper surface of the n+-type semiconductor layer; and
a Schottky electrode that forms a Schottky junction with the n−-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.