US 12,107,135 B2
Semiconductor device
Jung Gil Yang, Suwon-si (KR); Seung Min Song, Suwon-si (KR); Soo Jin Jeong, Suwon-si (KR); Dong Il Bae, Seongnam-si (KR); and Bong Seok Suh, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 7, 2021, as Appl. No. 17/467,660.
Application 17/467,660 is a continuation of application No. 16/732,520, filed on Jan. 2, 2020, granted, now 11,139,382.
Claims priority of application No. 10-2019-0059798 (KR), filed on May 22, 2019.
Prior Publication US 2021/0399108 A1, Dec. 23, 2021
Int. Cl. H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0642 (2013.01); H01L 29/4983 (2013.01); H01L 29/51 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first fin pattern and a second fin pattern separated by a fin trench, each of the first fin pattern and the second fin pattern extending lengthwise in a first direction;
a first nanosheet disposed on the first fin pattern;
a second nanosheet disposed on the second fin pattern;
a fin liner extending along at least a portion of a sidewall and a bottom surface of the fin trench;
a field insulation layer disposed on the fin liner and filling a portion of the fin trench;
a first gate structure overlapping an end portion of the first fin pattern;
a dummy gate structure on the field insulating layer and spaced apart from the first gate structure in the first direction; and
a first interlayer insulation layer between the first gate structure and the dummy gate structure,
wherein a height from the bottom surface of the fin trench to a lower surface of the dummy gate structure is greater than a height from the bottom surface of the fin trench to a lower surface of the first interlayer insulation layer,
wherein the first interlayer insulation layer includes a first portion overlapping the field insulation layer in the first direction, and a second portion on the first portion,
wherein the second portion of the first interlayer insulation layer overlaps the dummy gate structure in the first direction, and
wherein a maximum width of the first portion of the first interlayer insulation layer is greater than a maximum width of the second portion of the first interlayer insulation laver.