US 12,107,128 B2
Method of producing a semiconductor device having a ferroelectric gate stack
Saurabh Roy, Villach (AT); Thomas Aichinger, Faak am See (AT); and Hans-Joachim Schulze, Taufkirchen (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 5, 2023, as Appl. No. 18/461,042.
Application 18/461,042 is a division of application No. 17/387,504, filed on Jul. 28, 2021, granted, now 11,791,383.
Prior Publication US 2023/0411460 A1, Dec. 21, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 29/516 (2013.01); H01L 29/66053 (2013.01); H01L 29/78391 (2014.09)] 20 Claims
OG exemplary drawing
 
1. A method of producing a semiconductor device, the method comprising:
forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor, wherein forming each transistor cell of the plurality of transistor cells comprises forming a gate structure including a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and comprising a ferroelectric insulator, wherein the transistor has a specified operating temperature range; and
doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.