US 12,107,127 B2
Semiconductor device
Hiroshi Kono, Himeji Hyogo (JP); Teruyuki Ohashi, Kawasaki Kanagawa (JP); and Takahiro Ogata, Himeji Hyogo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Mar. 9, 2022, as Appl. No. 17/690,374.
Claims priority of application No. 2021-154761 (JP), filed on Sep. 22, 2021.
Prior Publication US 2023/0088612 A1, Mar. 23, 2023
Int. Cl. H01L 29/16 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1608 (2013.01) [H01L 29/0878 (2013.01); H01L 29/1095 (2013.01); H01L 29/7802 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first electrode;
a second electrode;
a gate electrode extending in a first direction;
a silicon carbide layer provided between the first electrode and the second electrode, having a first face parallel to the first direction on a side of the first electrode and a second face on a side of the second electrode, and including:
a first silicon carbide region of a first conductive type having a first region, a second region and a third region, the second region provided between the first region and the first face, the second region being in contact with the first face, the second region facing the gate electrode, the third region provided between the first region and the first face, the third region being in contact with the first face, and the third region being in contact with the first electrode;
a second silicon carbide region of a second conductive type provided between the first region and the first face, the second silicon carbide region disposed between the second region and the third region, the second silicon carbide region facing the gate electrode, and the second silicon carbide region electrically connected to the first electrode;
a third silicon carbide region of a second conductive type provided between the first region and the first face, the third silicon carbide region facing the gate electrode, and the third silicon carbide region electrically connected to the first electrode, the second region being disposed between the second silicon carbide region and the third silicon carbide region;
a fourth silicon carbide region of a second conductive type provided between the first region and the first face and electrically connected to the first electrode, the third region being disposed between the second silicon carbide region and the fourth silicon carbide region;
a fifth silicon carbide region of a first conductive type provided between the second silicon carbide region and the first face and electrically connected to the first electrode;
a sixth silicon carbide region of a second conductive type provided between the first region and the second silicon carbide region; and
a seventh silicon carbide region of a second conductive type provided between the first region and the second silicon carbide region, and the seventh silicon carbide region being separated from the sixth silicon carbide region in the first direction; and
a gate insulating layer provided between the gate electrode and the second silicon carbide region, the gate insulating layer provided between the gate electrode and the third silicon carbide region, and the gate insulating layer provided between the gate electrode and the second region.