CPC H01L 29/0649 (2013.01) [H01L 21/823481 (2013.01); H01L 21/823878 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01)] | 20 Claims |
17. An integrated circuit device, comprising:
a substrate comprising a first region and a second region spaced apart from each other;
a first fin-type active region defined by a first device isolation trench in the first region, the first fin-type active region comprising a first fin top surface at a first level;
at least one nanosheet on the first fin top surface;
a first gate line on the first fin-type active region, the first gate line surrounding the at least one nanosheet on the first fin top surface;
a second fin-type active region defined by a second device isolation trench in the second region, the second fin-type active region comprising a second fin top surface higher, relative to a bottom surface of the substrate, than the first fin top surface;
a second gate line on the second fin-type active region, the second gate line surrounding the second fin top surface and sidewalls of the second fin-type active region;
a first insulating structure on a sidewall of the first fin-type active region in the first region; and
a second insulating structure on a sidewall of the second fin-type active region in the second region,
wherein each of the first insulating structure and the second insulating structure comprises:
a lower buried insulating layer comprising a first top surface closer to a bottom surface of the substrate than the first level;
an upper buried insulating layer comprising a second top surface farther from the bottom surface of the substrate than the first top surface; and
an upper insulating liner between the lower buried insulating layer and the upper buried insulating layer.
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