US 12,107,122 B2
Integrated circuit devices
Sunki Min, Seoul (KR); Donghyun Roh, Suwon-si (KR); and Chaeho Na, Changwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 26, 2023, as Appl. No. 18/307,074.
Application 18/307,074 is a continuation of application No. 17/379,051, filed on Jul. 19, 2021, granted, now 11,670,676.
Claims priority of application No. 10-2020-0183522 (KR), filed on Dec. 24, 2020.
Prior Publication US 2023/0261047 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 21/823481 (2013.01); H01L 21/823878 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
17. An integrated circuit device, comprising:
a substrate comprising a first region and a second region spaced apart from each other;
a first fin-type active region defined by a first device isolation trench in the first region, the first fin-type active region comprising a first fin top surface at a first level;
at least one nanosheet on the first fin top surface;
a first gate line on the first fin-type active region, the first gate line surrounding the at least one nanosheet on the first fin top surface;
a second fin-type active region defined by a second device isolation trench in the second region, the second fin-type active region comprising a second fin top surface higher, relative to a bottom surface of the substrate, than the first fin top surface;
a second gate line on the second fin-type active region, the second gate line surrounding the second fin top surface and sidewalls of the second fin-type active region;
a first insulating structure on a sidewall of the first fin-type active region in the first region; and
a second insulating structure on a sidewall of the second fin-type active region in the second region,
wherein each of the first insulating structure and the second insulating structure comprises:
a lower buried insulating layer comprising a first top surface closer to a bottom surface of the substrate than the first level;
an upper buried insulating layer comprising a second top surface farther from the bottom surface of the substrate than the first top surface; and
an upper insulating liner between the lower buried insulating layer and the upper buried insulating layer.