| CPC H01L 27/14634 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 27/14636 (2013.01); H01L 27/14645 (2013.01); H01L 27/1469 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80894 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first structure including a first conductive pattern, the first conductive pattern exposed on a first surface of the first structure;
a second structure under the first structure, the second structure having a second surface that faces the first surface;
a mold layer on the first surface of the first structure, the mold layer covering an exposed surface of the first conductive pattern;
a first interlayer dielectric layer on the second surface of the second structure, the first interlayer dielectric layer being between the second structure and the mold layer;
a through via penetrating the second structure, the first interlayer dielectric layer and the mold layer, the through via electrically connected to the first conductive pattern, the through via including,
a first via segment in the second structure, and
a second via segment in the mold layer, the second via segment connected to the first via segment; and
a via insulation pattern including,
a first portion between the through via and the second structure,
a second portion between the through via and the mold layer, and
a third portion interposed between the second via segment and the first conductive pattern, the third portion including a part that horizontally extends, an edge of the part being vertically between the second via segment and the first conductive pattern.
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