CPC H01L 27/124 (2013.01) [G09G 3/2092 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); H01L 27/0207 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/0248 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/061 (2013.01); G09G 2320/0646 (2013.01); G09G 2320/0666 (2013.01)] | 6 Claims |
1. A semiconductor device comprising:
a pixel portion; and
a driver circuit electrically connected to the pixel portion, the driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the third transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a fifth wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor, and
wherein a gate of the sixth transistor is electrically connected to the sixth wiring.
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