a gate electrode arranged on a substrate; and

at least two active layer structures,

wherein the at least two active layer structures include a first active layer structure and a second active layer structure,

the first active layer structure includes a first conductive connection portion and a second conductive connection portion arranged oppositely, and a first oxide semiconductor pattern arranged between the first conductive connection portion and the second conductive connection portion, the first oxide semiconductor pattern is respectively coupled to the first conductive connection portion and the second conductive connection portion,

the second active layer structure includes a third conductive connection portion and a fourth conductive connection portion arranged oppositely, and a second oxide semiconductor pattern arranged between the third conductive connection portion and the fourth conductive connection portion, and the second oxide semiconductor pattern is respectively connected to the third conductive connection portion and the fourth conductive connection portion, and

an orthographic projection of the first oxide semiconductor pattern on the substrate and an orthographic projection of the second oxide semiconductor pattern on the substrate are both located within an orthographic projection of the gate electrode on the substrate, the second conductive connection portion is coupled to the third conductive connection portion;

wherein an orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the first oxide semiconductor pattern on the substrate have a first overlapping area;

an orthographic projection of the second conductive connection portion on the substrate and the orthographic projection of the first oxide semiconductor pattern on the substrate have a second overlapping area;

an orthographic projection of the third conductive connection portion on the substrate and the orthographic projection of the second oxide semiconductor pattern on the substrate have a third overlapping area;

an orthographic projection of the fourth conductive connecting portion on the substrate and the orthographic projection of the second oxide semiconductor pattern on the substrate have a fourth overlapping area;

the second overlapping area and the third overlapping area are located between the first overlapping area and the fourth overlapping area;

wherein the oxide thin film transistor further comprises a first lapping portion, and the second conductive connection portion and the third conductive connection portion are coupled to each other through the first lapping portion, and an orthographic projection of the first lapping portion on the substrate does not overlap the orthographic projection of the first oxide semiconductor pattern on the substrate, and does not overlap with the orthographic projection of the second oxide semiconductor pattern on the substrate;

wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern are sequentially arranged along a first direction, and are staggered along a second direction perpendicular to the first direction.