US 12,107,076 B2
Through-silicon via layout for multi-die integrated circuits
Wonjun Jung, Markham (CA); Jasmeet Singh Narang, Markham (CA); Tyrone Huang, Markham (CA); Christopher Klement, Markham (CA); Alan D. Smith, Santa Clara, CA (US); Edward Chang, Santa Clara, CA (US); and John Wuu, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed on Dec. 28, 2021, as Appl. No. 17/564,137.
Prior Publication US 2023/0207527 A1, Jun. 29, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/48 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first semiconductor die, including:
a first subset of a plurality of subsets of through-silicon vias (TSVs), wherein each TSV of the first subset is configured to transmit a first signal, and wherein the TSVs of the first subset are symmetrically arranged into quadrants of the first semiconductor die such that each TSV of the first subset is mirrored by another TSV of the first subset in each quadrant; and
a second subset of the plurality of subsets of TSVs, wherein each TSV of the second subset is configured to transmit a second signal, and wherein the TSVs of the second subset are symmetrically arranged into the quadrants such that each TSV of the second subset is mirrored by another TSV of the second subset in each quadrant.