| CPC H01L 23/535 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 19 Claims |
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1. A semiconductor device comprising:
a substrate including a cell array area and an extension area;
a lower memory stack disposed on the substrate and including a plurality of lower gate electrodes vertically stacked and spaced apart from one another, the lower memory stack including, at the extension area, a lower staircase structure in which the plurality of lower gate electrodes are stacked to have a staircase shape;
an upper memory stack disposed on the lower memory stack and including a plurality of upper gate electrodes vertically stacked and spaced apart from one another, the upper memory stack including, at the extension area, an upper staircase structure in which the plurality of upper gate electrodes are stacked to have a staircase shape;
a plurality of channel structures extending through the lower memory stack and the upper memory stack at the cell array area;
a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure;
an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer;
a plurality of lower contact plugs contacting the plurality of lower gate electrodes of the lower staircase structure; and
a plurality of upper contact plugs contacting the plurality of upper gate electrodes of the upper staircase structure,
wherein:
the lower interlayer insulating layer includes a first lower doping region extending along an upper surface of the lower staircase structure;
the upper interlayer insulating layer includes a first upper doping region extending along an upper surface of the upper staircase structure and an upper surface of the lower interlayer insulating layer, and the first upper doping region contacts the first lower doping region; and
a doping concentration of the first lower doping region is higher than a doping concentration of the first upper doping region.
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