a device layer including transistors on a substrate;

a plurality of wiring layers stacked on the device layer, the plurality of wiring layers including a lowermost wiring layer on the device layer, an uppermost wiring layer spaced furthest from the device layer, and at least one intermediate wiring layer between the lowermost and uppermost wiring layers;

a first through via passing through the substrate and the device layer, the first through via having an upper surface contacting a lower surface of the lowermost wiring layer; and

a second through via passing through the substrate, the device layer, the lowermost wiring layer, and the at least one intermediate wiring layer, the second through via having an upper surface contacting a lower surface of the uppermost wiring layer,

wherein a first height of the first through via is less than a second height of the second through via.