providing a first trench opening in a first area of an interlevel dielectric (ILD) material substrate formed in a semiconductor wafer, said first trench opening corresponding to a bottom electrode feature to be formed for contacting a top surface of a metal conductor wire formed in said ILD material substrate;

providing a second trench opening in a second area of said ILD material substrate formed in the semiconductor wafer, said second trench opening corresponding to an overlay/alignment mark feature to be formed which is deeper than the first trench opening, both said first and second trench opening formed through a diffusion barrier dielectric cap layer overlying a top surface of said ILD;

depositing a metal containing material layer for filling said first trench opening to form said bottom electrode to contact the top surface of the metal conductor wire, and said deposited metal containing material layer partially filling the second trench opening;

depositing a sacrificial material layer above said metal containing material layer, said sacrificial material layer completely filling an unfilled remaining portion of said second trench opening and extending above said second trench opening;

removing the sacrificial material layer and said metal containing material layer above and between said first trench opening and second trench opening, said sacrificial material layer and metal containing material layers remaining in said second trench opening; and

removing the sacrificial material layer in said remaining portion of said second trench opening, said partially filled second trench opening providing an overlay/alignment feature topography.