US 12,106,970 B2
Pattern sheet, semiconductor intermediate product, and hole etching method
Qiushi Xie, Beijing (CN); Xiaoping Shi, Beijing (CN); Qingjun Zhou, Beijing (CN); Dongsan Li, Beijing (CN); Chun Wang, Beijing (CN); and Yiming Zhang, Beijing (CN)
Assigned to BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
Appl. No. 17/919,520
Filed by BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
PCT Filed Apr. 2, 2021, PCT No. PCT/CN2021/085171
§ 371(c)(1), (2) Date Oct. 17, 2022,
PCT Pub. No. WO2021/208757, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 202010306855.2 (CN), filed on Apr. 17, 2020.
Prior Publication US 2024/0266182 A1, Aug. 8, 2024
Int. Cl. H01L 21/308 (2006.01); H01L 23/48 (2006.01)
CPC H01L 21/3081 (2013.01) [H01L 23/481 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A pattern sheet, comprising a first mask layer, a second mask layer, a dielectric layer, and a substrate sequentially arranged in stacks from top to bottom, wherein:
the first mask layer includes a first hole penetrating the first mask layer along a thickness direction of the first mask layer and satisfies:

OG Complex Work Unit Math
wherein, d1 denotes a thickness of the first mask layer, d2 denotes a thickness of the second mask layer, d4 denotes a thickness of the dielectric layer, S1 denotes an etching selectivity ratio of the substrate and the first mask layer, S2 denotes an etching selectivity ratio of the substrate and the second mask layer, S3 denotes an etching selectivity ratio of the dielectric layer and the first mask layer, S4 denotes an etching selectivity ratio of the dielectric layer and the second mask layer, and S5 denotes an etching selectivity ratio of the second mask layer and the first mask layer.