US 12,106,823 B2
Semiconductor device using transistors having low off-state current
Takeya Hirose, Atsugi (JP); Seiichi Yoneda, Isehara (JP); Takayuki Ikeda, Atsugi (JP); and Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/914,845
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Apr. 6, 2021, PCT No. PCT/IB2021/052826
§ 371(c)(1), (2) Date Sep. 27, 2022,
PCT Pub. No. WO2021/209858, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 2020-073841 (JP), filed on Apr. 17, 2020; and application No. 2020-076478 (JP), filed on Apr. 23, 2020.
Prior Publication US 2023/0147770 A1, May 11, 2023
Int. Cl. G11C 7/16 (2006.01); G11C 11/40 (2006.01); G11C 27/02 (2006.01); H01L 29/786 (2006.01); G11C 11/54 (2006.01)
CPC G11C 7/16 (2013.01) [G11C 11/40 (2013.01); G11C 27/02 (2013.01); H01L 29/786 (2013.01); G11C 11/54 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a first circuit, a second circuit and a source follower,
wherein the first circuit is configured to hold a first potential,
wherein the second circuit is configured to hold a second potential,
wherein the source follower is configured to output an output signal while the first potential and the second potential held in the first circuit and the second circuit are increased.