US 12,106,815 B2
Variable error correction codeword packing to support bit error rate targets
Ravi Motwani, Fremont, CA (US); Pranav Kalavade, San Jose, CA (US); Rohit Shenoy, Fremont, CA (US); and Rifat Ferdous, West Lafayette, IN (US)
Assigned to Intel Coproration, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 2, 2020, as Appl. No. 17/109,376.
Prior Publication US 2021/0082535 A1, Mar. 18, 2021
Int. Cl. G11C 16/04 (2006.01); G06F 12/0882 (2016.01); G11C 29/14 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G06F 12/0882 (2013.01); G11C 29/14 (2013.01); G11C 29/44 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
program a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density; and
program a second plurality of error correction codewords to a second set of pages in the block while bypassing the first set of pages, wherein the second plurality of error correction codewords are programmed at a second density, and the first density and the second density are to be different from one another.