US 12,106,811 B2
Semiconductor memory device
Yousuke Hagiwara, Kawasaki Kanagawa (JP); and Kei Shiraishi, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 5, 2022, as Appl. No. 17/882,459.
Claims priority of application No. 2022-058234 (JP), filed on Mar. 31, 2022.
Prior Publication US 2023/0317178 A1, Oct. 5, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/32 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a receiving unit that receives a first toggle signal from outside;
a first comparator that generates a second toggle signal switched in synchronism with the first toggle signal, and outputs the second toggle signal;
an adjustment unit that adjusts a duty cycle of the second toggle signal; and
a transmitting unit that transmits to the outside the second toggle signal with the adjusted duty cycle or a toggle signal generated based on the second toggle signal,
wherein:
the second toggle signal output from the first comparator includes a third toggle signal and a fourth toggle signal as a signal complementary to the third toggle signal,
the first comparator includes
a first input portion that receives the first toggle signal,
a second input portion that receives a reference signal,
a first output portion that outputs the third toggle signal switched according to a magnitude relationship between the first toggle signal and the reference signal, and
a second output portion that outputs the fourth toggle signal,
the adjustment unit includes a variable current source connected to at least one of the first input portion, the second input portion, the first output portion, and the second output portion, and
the adjustment unit adjusts an amount of current output from the current source to adjust a duty cycle of the second toggle signal.