US 12,106,810 B2
Memory device and asynchronous multi-plane independent read operation thereof
Jialiang Deng, Wuhan (CN); Zhuqin Duan, Wuhan (CN); Lei Shi, Wuhan (CN); Yuesong Pan, Wuhan (CN); Yanlan Liu, Wuhan (CN); and Bo Li, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 3, 2023, as Appl. No. 18/217,987.
Application 18/217,987 is a continuation of application No. 17/334,056, filed on May 28, 2021, granted, now 11,756,629.
Application 17/334,056 is a continuation of application No. PCT/CN2021/083505, filed on Mar. 29, 2021.
Prior Publication US 2023/0352100 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H03K 19/173 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/14 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
N memory planes, wherein N is an integer greater than 1;
M asynchronous multi-plane independent (AMPI) read units each configured to provide an AMPI read control signal for a respective memory plane of the N memory planes to control an AMPI read operation on the respective memory plane, wherein M is an integer smaller than or equal to N;
a first microcontroller unit (MCU) configured to provide a non-AMPI read control signal for each memory plane of the N memory planes to control a non-AMPI read operation on each memory plane; and
a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units and configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit of the M AMPI read units.