	US 12,106,803 B2
	Multi-step pre-read for write operations in memory devices
Yen Chun Lee, Boise, ID (US); Nevil N. Gajera, Meridian, ID (US); and Karthik Sarpatwari, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 25, 2022, as Appl. No. 17/824,776.
Application 17/824,776 is a continuation of application No. 17/154,644, filed on Jan. 21, 2021, granted, now 11,367,484.
Prior Publication US 2022/0284957 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4074 (2006.01); G11C 13/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)

CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0057 (2013.01); G11C 2013/0076 (2013.01)]

17 Claims

1. A device, comprising:

a memory array including memory cells;

bias circuitry configured to apply voltages to the memory cells;

sensing circuitry configured to determine states for the memory cells; and

a controller configured to:

apply, using the bias circuitry, at least one pre-read voltage to the memory cells; and

determine, using the sensing circuitry, an existing state for each of the memory cells;

wherein the controller is further configured to apply the pre-read voltage based on a physical location of the memory cells in the memory array.