| CPC G11C 11/409 (2013.01) [G11C 5/06 (2013.01); H10B 12/20 (2023.02); H10B 12/50 (2023.02)] | 14 Claims |
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1. A method for manufacturing a pillar-shaped semiconductor element-including memory device that controls voltages applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, a first impurity region, and a second impurity region to perform a data write operation, a data read operation, and a data erase operation,
the method comprising the steps of:
forming a first semiconductor pillar and a second semiconductor pillar standing on a substrate in a vertical direction and disposed adjacent to each other in a first direction in plan view, and a third semiconductor pillar and a fourth semiconductor pillar standing on the substrate in the vertical direction, having centers on a second line parallel to a first line passing through centers of the first semiconductor pillar and the second semiconductor pillar, and disposed adjacent to each other;
forming a first gate insulating layer surrounding lower portions of the first to fourth semiconductor pillars and a second gate insulating layer surrounding upper portions of the first to fourth semiconductor pillars,
a first gate conductor layer that surrounds the first gate insulating layer surrounding the first semiconductor pillar and the second semiconductor pillar and that extends between the first semiconductor pillar and the second semiconductor pillar,
a second gate conductor layer that surrounds the first gate insulating layer surrounding the third semiconductor pillar and the fourth semiconductor pillar and that extends between the third semiconductor pillar and the fourth semiconductor pillar,
a third gate conductor layer that surrounds the second gate insulating layer surrounding the first semiconductor pillar and the second semiconductor pillar and that extends between the first semiconductor pillar and the second semiconductor pillar, and
a fourth gate conductor layer that surrounds the second gate insulating layer surrounding the third semiconductor pillar and the fourth semiconductor pillar and that extends between the third semiconductor pillar and the fourth semiconductor pillar;
before or after the forming of the first to fourth semiconductor pillars, forming the first impurity region connected to bottom portions of the first to fourth semiconductor pillars;
before or after the forming of the first to fourth semiconductor pillars, forming the second impurity region in a top portion of each of the first to fourth semiconductor pillars; and
forming a first wiring conductor layer connected to the second impurity region of each of the top portions of the first semiconductor pillar and the third semiconductor pillar, and a second wiring conductor layer connected to the second impurity region of each of the top portions of the second semiconductor pillar and the fourth semiconductor pillar.
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