| CPC G11C 11/4085 (2013.01) | 20 Claims |
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1. A memory device comprising:
a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction; and
a second sub wordline driver including
a second active region connected to a second wordline through a second direct contact, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction, and
a second transistor connected to a second gate line, the second gate line extending in the first direction,
wherein a third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.
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