| CPC G11C 11/4076 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 7/222 (2013.01); G11C 11/409 (2013.01)] | 20 Claims |
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1. A method for performing a duty adjustment operation in a memory system, the method comprising:
transmitting, by a memory controller, a write clock and a control command to a synchronous dynamic random access memory (SDRAM) device;
generating, by the SDRAM device, an internal write clock based on the write clock;
performing, by the SDRAM device, a duty monitoring operation on the internal write clock in response to the control command for generating a duty monitoring information;
storing the duty monitoring information in a first mode register set (MRS); transmitting, by the SDRAM device, the duty monitoring information to the memory controller;
generating, by the memory controller, a duty control signal based on the duty monitoring information;
transmitting, by the memory controller, the duty control signal;
storing the duty control signal in a second MRS of the SDRAM device; and
performing, by the SDRAM device, the duty adjustment operation on the internal write clock using the duty control signal stored in the second MRS for generating a duty adjusted internal write clock,
wherein the duty control signal includes a polarity of a duty cycle adjustment with which the memory controller decides whether to increase a portion of logic level high of the internal write clock or to increase a portion of logic level low of the internal write clock.
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